1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of forming a contact plug having a reduced contact resistance, preferably adaptable to the fabrication of highly-integrated semiconductor device or a system integrated circuit device.
2. Description of the Prior Art
Recently, the more a semiconductor device is integrated, the more a design rule for realization of the device is reduced. According to such a trend, various processes have been developed, introduced and adopted to obtain better characteristics for the device. Recent developments in contact processes have been widely made to reduce contact resistance, thus improving operational efficiency of the device.
In general, the conventional semiconductor device has a silicon contact material based upon a polysilicon doped with impurities.
If contact were made in an ideal interface state between a silicon substrate and a polysilicon layer, the contact resistance due to the difference in work function would not actually exist in the contact interface established with the same material. Furthermore, when respective impurity concentrations are alike in the silicon substrate and the polysilicon layer, the contact resistance therebetween may be very low.
However, in fact, the contact resistance between the silicon substrate and the polysilicon layer is relatively high.
For example, a contact junction cell having a contact area of 0.10 square microns has a contact resistance of about ten kilo-ohms.
Such a high contact resistance is known in the art to be caused by a native oxide layer and a residue, including carbon, both of which are unfortunately formed in the interface between the silicon substrate and the polysilicon layer.
To remove in advance the native oxide layer and the carbon residue, a conventional polysilicon contact process is performed as soon as a wet cleaning process is completed. However, the high contact resistance is not effectively reduced as expected.
The wet cleaning process currently used in conventional methods has a final cleaning step using a volatile deorganic compound solution and deionized water. This is one of reasons why the removal of the native oxide layer and the carbon residue is not effective.
In recent years, a selective epitaxial growth technique of single crystalline silicon has been proposed as an alternative approach to overcome the increase in resistance due to reduced contact area. The selective epitaxial growth technique serves to increase of resistance resulting from the natural oxide layer and grain boundary in the contact interface.
The selective epitaxial growth technique uses mostly a low-pressure chemical vapor deposition (LPCVD) process. In addition, the LPCVD process employs a reaction gas system composed of dichlorosilane (DCS), H2 and HCl, or monosilane (MS), H2 and HCl.
Furthermore, a high temperature process over about 800° C. is required for the selective epitaxial growth of single crystalline silicon. However, the high temperature process is one of the causes of difficulty in guaranteeing the precise definition of device characteristics.
Accordingly, there exists a strong need for an improved process which can grow single crystal silicon with low contact resistance at the lowest possible temperature.